The present invention relates to clock distribution circuits for use in distributing a clock signal to a plurality of locations in a circuit where the circuit elements at each of the plurality of locations are synchronous circuits that operate using the clock signal.
One approach to clock distribution on an integrated circuit or circuit board is to lay out traces to route the clock signal to each circuit element that needs to be clocked. Where there are a large number of clocked elements, such as hundreds or more, the clock signal is often applied to a fan-out tree, with a clock input feeding a fan-out device that outputs a plurality of clock signals, which are in turn inputs to other fan-out devices.
At each fan-out device, the clock signal might be amplified by a transistor circuit. When the clock signal transitions, such as from high to low or low to high, the transistor circuit would change state, so that its outputs change state to propagate the clock signal. The clocked circuits also typically contain transistors or other active devices that switch in response to a clock transition. Each of these circuits draws some current from a power supply when it switches, and if all these circuits switch at the same time, the peak current drawn from the supply can be many times greater than the current drawn at other times in the clock cycle. If the power supply has to be designed to handle the peak current and the peak current is much larger than the average current, the power supply might need to be larger just to handle the peak current.
Another undesirable effect of a clocked circuit is that the peak electromagnetic radiation from an electronic device having many clocked circuits is often much larger than the average electromagnetic radiation, due to the increased electrical activity at the clock transitions.